1. Field of the Invention
The present invention relates to transfer of data packets through a node in a telecommunications system, and, in particular, to merging packets of one or more virtual circuits into a single output data stream.
2. Description of the Related Art
Telecommunication systems typically employ a hierarchy to integrate multiple user data channels for transmission through a medium. Transmission through the medium at one level of the hierarchy is generally at a much higher rate than the rate of each user's data at a lower level of the hierarchy. Synchronous networks, such as cell relay (ATM or SONET) networks, may use a format in which data packets of individual virtual circuits (VCs) are merged into a single output stream. Similarly, data packets of VCs may be grouped at a system level according to traffic class. Data packets of VCs may be merged for each class into traffic class data streams, and these traffic class data streams are then merged into the single output stream.
FIG. 1 shows an exemplary prior art implementation for merging data packets of several VCs. Reassembly buffers 101–104 receive cells of data packets for corresponding VCs VC1–VC4. When cells of a complete packet are received into one of the reassembly buffers 101–104, a corresponding flag is set. VC merge server 105 performs a merge operation by continually checking and serving those reassembly buffers 101–104 having a flag set indicating that a full packet is present within the buffer. For example, VC merge server 105 may include a buffer server and a scheduler (not shown) that may implement a method of round-robin scheduling. A buffer service by VC merge server 105 moves one or more packets from one of the reassembly buffers 101–104 to output buffer 106. The data packets of the VCs VC1–VC4 are thus merged into the output buffer 106, and the contents of output buffer 106 is emptied (read out) as the single output stream.
Each data packet of a VC generally comprises one or more cells, with the last cell of the packet having a flag set to indicate that it is the end of packet (EOP) cell. Building a packet refers to the process of receiving the cells of a complete packet. Some data packets are quite long, and under some conditions, such as when there are many active VCs, VC merge server 105 may take longer to serve each reassembly buffer. Under these conditions, a reassembly buffer may overflow. An overflow of the buffer occurs when a cell input to the reassembly buffer exceeds this threshold before receiving the EOP cell. The reassembly buffers 101–104 are gated after a threshold (e.g., buffer length) is reached. When the threshold is reached, prior art implementations may either 1) drop the remaining cells of the packet being built, with the exception of the EOP packet, or 2) let the current packet finish being built (receive all cells up to the EOP cell) before denying access to future cells. In either case, the output stream includes the FOP cell for the currently built packet. If interveaning cells are dropped, the system allows corrupted packet information to pass to the output stream, thus wasting available capacity. If the system allows the current packet to finish being built, with very long packets, the reassembly buffer length may not be adequate to allow the packet to finish being built. Thus, to handle very long packets, the length of the reassembly buffer may be excessively long beyond the threshold, wasting available buffer capacity.